Modeling the Effect of Wire Resistance in Deep Submicron Coupled Interconnects for Accurate Crosstalk Based Net Sorting

It is well known that in deep submicron technologies the coupling capacitance between adjacent wires is a critical portion of the total wire capacitance, while at the same time the capacitance between wire and substrate has become the fringing component. High frequency signals travelling across multiple level interconnect structures generate proximity effects, i.e. crosstalk effects, between adjacent wires. Such effects include delay and noise injection and are a serious performance limitation in deep submicron VLSI circuits. An analytical model of the crosstalk effects would be extremely useful both in the design front-end and in the design back-end. For instance, a net ranking procedure based on such model could efficiently identify potential signal integrity problems between nets. A compact model of the coupled noise pulse amplitude which improves considerably the simple charge sharing model has been proposed in [4]. In our paper we will demonstrate that such model turns out to be quite inaccurate in several cases that often occur in practical circuits, because it does not consider the wire resistance. Moreover we will introduce an heuristic technique that allows to take into account the resistive effects, thus achieving a considerable accuracy improvement at an equivalent computational cost. I Introduction Coupling effects between adjacent interconnect lines represent a serious limitation to performances and functionality of high speed electronic systems [1], [2], [3]. Therefore the verification of the crosstalk effects on signal integrity and delay, along with design techniques that minimize such effects by construction, are of the utmost importance in deep submicron VLSI circuit design. The availability of an efficient estimator of the impact of coupled noise on a given signal is a crucial element for crosstalk avoidance during the routing phase and for crosstalk aware timing verification techniques. Because of the huge number of interconnect lines in industrial VLSI designs, it is impractical to apply an accurate dynamic delay back-annotation including coupled noise on every net. Therefore a preliminary screening of the potentially crosstalk prone nets is needed. Usually this is done by using a simple charge sharing model, thus yielding the following equation for the coupled noise voltage amplitude [3]: